The invention relates generally to integrated electronic circuits which utilize digital information processing devices to generate a desired output based upon information received at a circuit's input and/or as programmed. More specifically this invention relates to an integrated electronic circuit for comparing at least two digital values and, in the event such values are equal, providing at least two non-equal outputs.
A specific implementation of the invention is for use in integrated chips employing a pulse width modulated (PWM) signal to avoid 100% duty cycling. It is general practice for a designer of an integrated chip to utilize a PWM signal to carry out various IC circuit functions. The PWM pulse is defined by period and duty cycle components, the values of which are commonly desired to be non-equal. When both period and duty cycle component values are equal, 100% duty cycling occurs.
A previous method of detecting and avoiding 100% duty cycling was to compare the duty cycle and period values and, in the event that they were equal, either increment or decrement one or the other value by one. In addition to a comparator, this implementation requires an adder which adds a one to the first value or a subtractor (two's complement with adder) which subtracts a one from the second value. Generally, such circuits are dealing with multi-bit values and the modification of adding or subtracting one to the least significant bit of a value would potentially result in effecting a change in all bits associated with that value.
For example, in the case of an incrementer implementation where a seven-bit value represents a duty cycle of 6F in hexadecimal and a second seven-bit value represents a period of 6F, all seven-bits of the period register would require modification to change it to 70. This implementation additionally requires the use of an overflow control circuit for use when the duty cycle and period values are 7F. As another example, in the case of a decrementer implementation where the first seven-bit value represents a period of 70 and the second seven-bit value represents a duty cycle of 70, all 7-bits of the duty cycle register would require modification to change it to 6F. Circuits utilizing the decrementer implementation require converting the duty cycle value to its two's complement, adding one, and converting that value to its two's complement. This implementation also requires a control circuit for underflow conditions such as when the duty cycle and period values are each 00.